In the design of high performance random access memories (RAMS) the use of a negative substrate bias voltage has become common. To minimize the printed circuit board space required for using the devices, it is desirable to generate the substrate bias voltage on the chip. One regulator circuit for providing a substrate bias voltage is described in pending U.S. patent application Ser. No. 017,523, now abandoned, filed Mar. 5, 1979, and assigned to the assignee of the instant invention.
The characteristics of present on-chip regulators result in certain problems in the operation of high performance RAMS. Typically, in high performance RAMS there is a portion of a read or write cycle during which all of the bit sense lines are precharged to the supply voltage or very close to it. During another portion of the cycle, called the active portion of the cycle, when the read or write function is actually performed, one half of the bit sense lines are discharged in an action for performing the read or write. A bit sense line in a typical memory device has a large parasitic capacitance to the substrate which couples the precharging and discharging current to the substrate. Because on-chip substrate bias voltage regulators typically have high output impedance, the coupling of the precharging and discharging currents to the substrate via stray capacitance has a significant effect on the substrate voltage.
When one half the lines are discharged, the substrate voltage is lowered to a more negative voltage. A typical substrate bias voltage regulator has a pump which operates to drive the substrate to a negative voltage. When the substrate reaches the desired negative voltage, the pump is turned off. When the substrate rises above the desired voltage, the pump is turned back on until the desired level is reached again. As a consequence of this type of operation, when the substrate is approximately at the desired level and a discharge of one half of the bit sense lines occurs which drives the substrate significantly more negative than the desired level, the regulator does not have any way of bringing the substrate back up to the desired level other than through leakage current and current through a control circuit to the substrate which is intentionally minimized. Consequently the substrate voltage varies during virtually the entire active portion of the cycle, the time when information is being either read or written. Because device characteristics vary with substrate bias voltage, it is important to have a steady substrate bias voltage.
When the bit sense lines are precharged, the substrate bias voltage is raised which has one of the potential dangers of forward biasing P/N junctions which exist between the substrate, which may be of a P-doped material, and source and drain which may be of an N-doped material, of the transistors. One of the purposes of providing a negative substrate bias voltage is to avoid forward biasing which injects carriers into the substrate where they can migrate to the memory cell array with the potential of causing the loss of information stored therein. When the active portion of the cycle is long compared to the precharge portion over a sufficient number of cycles to allow the substrate bias voltage to reach a regulated level during the active portion, the consequent positive shift due to precharging then brings the substrate bias voltage to the level which will present the highest danger of forward biasing P/N junctions.
To compensate for the discharge of one half of the bit sense lines by providing dummy lines to charge simultaneously to exactly offset the effect of the discharge, requires a substrate increase in chip area which, of course, is undesirable. To provide a substrate bias voltage generator with sufficiently low output impedance to render the shifts in substrate voltage negligible would also require very significant increases in chip area as well as a substantial increase in the total power dissipation of the RAM.
The instant invention provides a practical solution to providing a more efficient on-chip substrate bias voltage regulator, one objective of which is to hold the substrate bias voltage at a relatively constant level during the active portion of the cycle and another objective of which is to maintain the substrate bias voltage sufficienty negative to ensure that the P/N junctions, of which the substrate is part, are forward biased.